Quartus 25.3 Upgrade Issue: Ghrd-socfpga Project Fails
Are you struggling to upgrade your project to Quartus 25.3? You're not alone! This article dives into a common problem encountered when trying to upgrade the ghrd-socfpga project to the latest Quartus version, specifically 25.3. We'll dissect the error logs, understand the root causes, and explore potential solutions to get your project up and running smoothly. If you're an FPGA developer working with Intel's Quartus Prime software and facing upgrade challenges, this guide is for you.
Understanding the Quartus 25.3 Upgrade Error
When attempting to upgrade a project, particularly the ghrd-socfpga, to Quartus 25.3, users may encounter a series of errors during the IP core generation process. The error logs, as shown below, provide valuable clues about the nature of the problem. Let's break down the key issues:
First, the process begins by cloning the ghrd-socfpga repository and checking out a specific release:
$ git clone https://github.com/ArrowElectronics/ghrd-socfpga
$ git checkout QPDS25.1_REL_GSRD_PR
This step ensures that we're working with a known and stable version of the project.
Decoding the Error Log
The error log is a treasure trove of information, but it can be intimidating at first glance. Key sections to pay attention to include:
- IP Core Backup: The system diligently backs up existing IP core files before attempting the upgrade. This is a crucial safety measure, ensuring that you can revert to the previous state if something goes wrong. These backups are indicated by the
.BAK.ipextension.
Info(11902): Backing up file "/home/user/project/ghrd-socfpga/axe5_eagle_ghrd/ip/hps_system/ace5lite_cache_coherency_translator.ip" to "/home/user/project/ghrd-socfpga/axe5_eagle_ghrd/ip/hps_system/ace5lite_cache_coherency_translator.BAK.ip"
- Quartus Prime Information: The log provides standard information about the Quartus Prime software, including copyright notices and license agreement details. This section confirms that the software is running and provides a link to the End User License Agreement (EULA).
Info(20325): ***************************************************************
Info(20325): Quartus is a registered trademark of Intel Corporation in the
Info(20325): US and other countries. Portions of the Quartus Prime software
Info(20325): code, and other portions of the code included in this download
Info(20325): or on this DVD, are licensed to Intel Corporation and are the
Info(20325): copyrighted property of third parties. For license details,
Info(20325): refer to the End User License Agreement at
Info(20325): http://fpgasoftware.intel.com/eula.
Info(20325): ***************************************************************
- IP Core Upgrade Process: The log details the steps taken to upgrade IP cores within the Platform Designer system. This involves upgrading individual IP cores, generating simulation models and scripts, and creating block symbol files.
Info(20325): 2025.11.14.11:53:13 Info: Starting to upgrade the IP cores in the Platform Designer system
Info(20325): 2025.11.14.11:53:13 Info: Finished upgrading the ip cores
- Warnings: Warnings indicate potential issues that may not necessarily halt the process but should be investigated. For example:
Warning(20326): 2025.11.14.11:54:12 Warning: Skipping generation of synopsys/vcs/vcs_setup.sh since VCS 2-step flow is not supported for specified device family. Use VCS-MX or another supported simulator.
This warning suggests that the Synopsys VCS 2-step flow is not supported for the target device family, and the user should consider using VCS-MX or another compatible simulator.
- Errors: Errors, on the other hand, are critical and prevent the upgrade process from completing. These need to be addressed to successfully upgrade the project. We see several errors in this log, which we will analyze in detail.
Diving Deep into the Errors
The error log reveals several specific issues that prevent the project from upgrading successfully. Let's examine each of them:
- emif_bank3a_hps Errors: These errors point to problems with the
emif_bank3a_hpsIP core, specifically related to the